Problème Verilog avec instruction case/always

Question

J'ai codé ce module pour la classe en utilisant l'exemple de code donné, mais je reçois des erreurs en essayant de compiler - je pense que cela est dû à la façon dont j'utilise les entrées (Ou juste une erreur de syntaxe), donc j'essaye de le faire avec des tableaux - Mon approche commentée est-elle correcte? Suis-je censé utiliser la concaténation?

module ledSwitch(LEDR, SW); 
    input [9:0] SW; //switches and led 
    output [0] LEDR; 

    mux7to1 u0(
     .s0(SW[0]),//input switches to mux 
     .s1(SW[1]), 
     .s2(SW[2]), 
     .s3(SW[3]), 
     .s4(SW[4]), 
     .s5(SW[5]), 
     .s6(SW[6]), 
     .s7(SW[7]), 
     .s8(SW[8]), 
     .s9(SW[9]), 
     //.inputs([SW[0], [SW[1], [SW[2], [SW[3], [SW[4], [SW[5], [SW[6]]) 
     //.muxSelect([SW[7], [SW[8], [SW[9]) 
     .l(LEDR[0]) //input led output to mux 
     ); 
endmodule 

module mux7to1(s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, l); 
    input s0; 
    input s1; 
    input s2; 
    input s3; 
    input s4; 
    input s5; 
    input s6; 
    input s7; 
    input s8; 
    input s9; 
    //input inputs[6:0] 
    //input muxSelect[2:0] 

    output l; 

    reg Out; //declare the output signal for the always block 

    always@(*) //declare always block 
    begin 
     case ([s9, s8, s7])//muxSelect[2:0] //start case statement 
      3'b000: Out = s0; //case 0, A 
      3'b001: Out = s3; //case 1, D 
      3'b010: Out = s1; //case 2, B 
      3'b011: Out = s5 //case 3, F 
      3'b100: Out = s0; //case 4, A 
      3'b101: Out = s4; //case 5, E 
      3'b110: Out = s2; //case 6, C 
      3'b111: Out = s6; //case 7, G 
      default: Out = 0; //Default   
     endcase 
    end 
    assign l = Out; 
endmodule 

Voici le message d'erreur:

Info: *******************************************************************

Info: Running Quartus II 64-Bit Analysis & Synthesis

Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition

Info: Processing started: Tue Feb 2 14:53:06 2016

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab2_1 -c Lab2_1

Warning (20028): Parallel compilation is not licensed and has been disabled

Error (10170): Verilog HDL syntax error at Lab2_1.v(43) near text "["; expecting an operand

Error (10170): Verilog HDL syntax error at Lab2_1.v(45) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(46) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(47) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(48) near text "3"; expecting ";"

Error (10170): Verilog HDL syntax error at Lab2_1.v(49) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(50) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(51) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(52) near text "default"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(53) near text "endcase"; expecting "end"

Error (10112): Ignored design unit "mux7to1" at Lab2_1.v(24) due to previous errors

Info (12021): Found 0 design units, including 0 entities, in source file Lab2_1.v

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 11 errors, 1 warning

Error: Peak virtual memory: 959 megabytes

Error: Processing ended: Tue Feb 2 14:53:23 2016

Error: Elapsed time: 00:00:17

Error: Total CPU time (on all processors): 00:00:51

Error (293001): Quartus II Full Compilation was unsuccessful. 13 errors, 1 warning

Answer 1

Vous devez utiliser l'opérateur de concaténation: case ({s9, s8, s7})

vous avez également quelques erreurs de syntaxe, comme la disparition des points-virgules que vous devez corriger. Enfin, dans le module ledSwitch, vous devez définir correctement la sortie.