Modelsim "Entity '...' n'a pas d'architecture." erreur

Question

Je suis en train de simuler un projet VHDL mais ModelSim me donne le message d'erreur suivant:

Error: (vsim-3173) Entity 'C:/Users/chose/Documents/CTD/teste/SELETORES/simulation/modelsim/rtl_work.seletores' has no architecture. 

I tryed creatindg un autre projet et il me donne la même erreur. J'étais capable de simuler d'autres projets avant, en faisant la même chose. J'utilise Quartus Prime Lite Edition 16.0 et Modelsim 10.5b. Le code que j'essaie de simuler est:

library IEEE; 
use IEEE.Std_Logic_1164.all; 

entity SELETORES is 
port( IN_POT: in std_logic; 
     OUT_POT, REG_ALARM, REG_OPEN, CONTA, SW 
       : in std_logic_vector(9 downto 0); 
     MODE : in std_logic_vector(39 downto 0); 
     SEL_DISP, SEL_LED 
       : in  std_logic_vector(1 downto 0); 
     LED_OUT, SEL_TIME, SEL_POT 
       : out std_logic_vector(9 downto 0); 
     REG : out std_logic_vector(19 downto 0) 
     ); 
end SELETORES; 

architecture SELETORES_bhv of SELETORES is 
    signal decod_mux : std_logic_vector(19 downto 0); 

component mux_4x1_20 
port (W,X,Y,Z: in std_logic_vector(19 downto 0); 
     S: in std_logic_vector(1 downto 0); 
     F: out std_logic_vector(19 downto 0) 
    ); 
end component; 

component mux_4x1_10 
port (W,X,Y,Z: in std_logic_vector(9 downto 0); 
     S: in std_logic_vector(1 downto 0); 
     F: out std_logic_vector(9 downto 0) 
    ); 
end component; 

component mux_2x1 
port (W,X: in std_logic_vector(9 downto 0); 
     S: in std_logic; 
     F: out std_logic_vector(9 downto 0) 
    ); 
end component; 

component decod_time 
port( ENTRADA : in std_logic_vector(9 downto 0); 
     SAIDA: out std_logic_vector(19 downto 0) 
     ); 
end component; 

begin 

L1 : mux_4x1_10 port map ("0000000000", REG_OPEN, OUT_POT, REG_ALARM, SEL_LED, LED_OUT); 

L2 : mux_2x1 port map (SW, MODE(19 downto 10), SEL_DISP(0) and not(SEL_DISP(1)), SEL_TIME); 

L3 : decod_time port map (CONTA, decod_mux); 

L4 : mux_4x1_20 port map ("00000110010111101111", MODE(39 downto 20), decod_mux, "11111100011100111101", SEL_DISP, REG); 

L5 : mux_2x1 port map (SW, MODE(9 downto 0), IN_POT, SEL_POT); 

end SELETORES_bhv; 

Answer 1

Tout d'abord vous avez quelques erreurs de syntaxe dans votre instanciation de composant L2. En second lieu, à mon avis, c'est la bonne façon de le faire (les opérateurs ne sont pas autorisés dans les cartes portuaires):

library IEEE; 
use IEEE.std_logic_1164.all; 

entity SELETORES is 
port( IN_POT: in std_logic; 
     OUT_POT, REG_ALARM, REG_OPEN, CONTA, SW 
       : in std_logic_vector(9 downto 0); 
     MODE : in std_logic_vector(39 downto 0); 
     SEL_DISP, SEL_LED 
       : in  std_logic_vector(1 downto 0); 
     LED_OUT, SEL_TIME, SEL_POT 
       : out std_logic_vector(9 downto 0); 
     REG : out std_logic_vector(19 downto 0) 
     ); 
end SELETORES; 

architecture SELETORES_bhv of SELETORES is 

-- Component declarations 

component mux_4x1_20 
    port (W,X,Y,Z: in std_logic_vector(19 downto 0); 
     S1: in std_logic_vector(1 downto 0); 
     F: out std_logic_vector(19 downto 0) 
     ); 
end component; 

component mux_4x1_10 
    port (W,X,Y,Z: in std_logic_vector(9 downto 0); 
     S2: in std_logic_vector(1 downto 0); 
     F: out std_logic_vector(9 downto 0) 
     ); 
end component; 

component mux_2x1 
    port (W,X: in std_logic_vector(9 downto 0); 
     S3: in std_logic; 
     F: out std_logic_vector(9 downto 0) 
     ); 
end component; 

component decod_time 
    port(ENTRADA : in std_logic_vector(9 downto 0); 
     SAIDA: out std_logic_vector(19 downto 0) 
     ); 
end component; 

--End component declarations 

-- Internal signals 

signal decod_mux : std_logic_vector(19 downto 0); 
signal foobar: std_logic; 

--End Internal Signals 

begin 

foobar <= SEL_DISP(0) AND NOT SEL_DISP(1); 

L1 : mux_4x1_10 port map ("0000000000", REG_OPEN, OUT_POT, REG_ALARM, SEL_LED, LED_OUT); 

L2 : mux_2x1 port map (SW, MODE(19 downto 10), foobar, SEL_TIME); 

L3 : decod_time port map (CONTA, decod_mux); 

L4 : mux_4x1_20 port map ("00000110010111101111", MODE(39 downto 20), decod_mux, "11111100011100111101", SEL_DISP, REG); 

L5 : mux_2x1 port map (SW, MODE(9 downto 0), IN_POT, SEL_POT); 

end SELETORES_bhv; 

Je l'ai testé sur ModelSim 10.1c sans problème.